1. Field of the Invention
The present invention relates to a semiconductor device which is useful for the application to a BiCMOS transistor wherein a bipolar transistor and a CMOS transistor are intermixed, and a process for fabricating the same; and in particular to a semiconductor device wherein a bipolar transistor is improved, and a process for fabricating the same.
2. Description of the Prior Art
Recently, it has been demanded to improve the performance of an analogue/digital intermixing LSI (large scale integrated circuit), wherein an analogue circuit and a digital circuit are mounted inside a single chip, and reduce costs thereof with rapid popularization of a personal handy system (PHS), a portable telephone, a communication terminal for a network, and the like.
In general, a CMOS transistor, which can easily make its consumption electric power small, is used as a digital circuit corresponding to high-speed action in the analog/digital intermixing LSI. As an analogue circuit corresponding to high-speed action, a high-performance bipolar transistor is used, and the action of the circuit is performed at a high frequency of several hundreds of MHz to several tens of GHz. Therefore, in order to use the analogue circuit at higher frequencies, it is necessary to improve high frequency characteristics of the bipolar transistor.
As indexes of AC characteristics of the bipolar transistor, fT (cut-off frequency) and fmax (maximum oscillation frequency) are known. Especially, the maximum oscillation frequency fmax, which is an index of driving ability of the bipolar transistor, is a factor for estimating main characteristics of the bipolar transistor. This fmax is approximately represented by the following formula:
fmax≈{square root over ( )}(fT/(8xcfx80xc2x7Rbxc2x7Ccb))
wherein Rb represents a base resistance, and Ccb represents a capacity between collector and base (base-to-collector capacitance).
The expression representing the fmax includes fT, as is clearly from the formula 1. Therefore, the fmax shows the total performance of the high frequency characteristics of the bipolar transistor. It can be said that as this value is larger, the high frequency characteristics are better.
Incidentally, it can be understood from this formula 1 that in order to heighten the fmax, it is effective to improve the cut-off frequency fT, and reduce the base resistance Rb and the collector-base capacity.
The following will describe a conventional method for reducing the base resistance Rb and improving the fmax. The conventional technique for reducing the base resistance is described in pages 807 to 810 of 1997 IEDM (International Electron Device Meeting) Technical Digest.
FIG. 1 is a plan view showing an arrangement of respective layers of a conventional bipolar transistor. FIG. 2 is a sectional view taken along Fxe2x80x94F line of FIG. 1. FIG. 3 is a sectional view taken along Gxe2x80x94G line of FIG. 1. As shown in FIGS. 1-3, in the conventional bipolar transistor a high-concentration N type buried layer 503 is formed on a P type semiconductor substrate 501. Moreover, an N type epitaxial area 504 is formed to cover the buried layer 503. In the N type epitaxial area 504, a pedestal collector 512, which is an N type area having an impurity concentration that is in the middle of concentrations of the epitaxial area 504 and the buried layer 503, is formed just under a high-concentration N type diffusion layer 520, which is an emitter region. In this way, the collector area of the bipolar transistor is composed of the high-concentration N type buried layer 503, the N type epitaxial area 504 and pedestal collector 512.
An element separation oxide film 506 is formed in the surface of the N type epitaxial area 504. This element isolation oxide film 506 is formed to surround an intrinsic base region 509, a high-concentration P type diffusion layer 518, and a high-concentration N type diffusion layer 519. The intrinsic base region 509 and the high-concentration P type diffusion layer 518 are electrically isolated from the high-concentration N type diffusion area 519 by means of the element isolation oxide film 506. A high-concentration N type diffusion layer 520 is formed inside the intrinsic base region 509. This high-concentration N type diffusion layer 520 makes an emitter region. An emitter leading-out electrode 513 made of polysilicon is formed to connect this emitter region. A titanium silicide film 521 is formed on the surface of this emitter electrode 513. The titanium silicide film 521 is also formed on the surface of the high-concentration P type diffusion layer 518 to make an extrinsic base region (a graft base region). The surface of a collector plug region, which is composed of the high-concentration N type diffusion layer 519, is also covered with the titanium silicide film 521. An interlayer dielectric 522 is formed on its whole surface. In this interlayer dielectric 522, base contact holes 524 are made in its extrinsic base region, and a contact hole 525 for collector plug is made in the collector plug region. An emitter contact hole 526 is made in the interlayer dielectric 522 just above the emitter electrode.
The following will describe the form of a plan view arrangement of the above-mentioned conventional bipolar transistor. In this bipolar transistor, the high-concentration P type diffusion layer 518, the surface of which is covered with the titanium silicide film 521, is divided into right and left portions in FIG. 21 by means of the emitter leading-out electrode 513 composed of the second conductive film, the surface of which is covered with the titanium silicide film 521. The base contact holes 524 are made at right and left positions adjacent to the emitter leading-out electrode 513 composed of the second conductive film, so as to make a form of the arrangement for leading out a non-illustrated metal wiring for leading-out of the base electrode.
The plan view layout according to this method is as follows: the surface of the high-concentration P type diffusion layer 518 is covered with the titanium silicide film having a sheet resistance of about 5 xcexa9/square and the non-illustrated metal wiring for leading-out of the base electrode is led out at both ends of the emitter leading-out electrode 513 composed of the second conductive film. Therefore, this layout makes it possible to make the base resistance lower than the layout wherein the surface of the high-concentration P type diffusion layer 518 is not covered with any titanium silicide. The above-mentioned known publication states that for this reason the maximum oscillation frequency fmax can be raised up to 54 GHz when the voltage between the collector and the emitter (C-E voltage) is 2.5 V.
The following will describe an example of a process for fabricating the above-mentioned conventional bipolar transistor, referring to FIGS. 4-10.
As shown in FIG. 4, the high-concentration N type buried layer 503 is formed on the P type semiconductor substrate 501. The N type epitaxial area 504 of 1 xcexcm in thickness is formed on the P type semiconductor substrate 501 to cover the high-concentration N type buried layer 503.
Next, as shown in FIG. 5, the element isolation oxide film 506 is formed on the epitaxial area 504 by the LOCOS (Local oxidation of Silicon) method. Furthermore, the first oxide film 505 is formed on the epitaxial area 504 to have a thickness of 12 nm.
Next, as shown in FIG. 6, the high-concentration N type diffusion layer 519 is formed, in the portion which becomes the collector plug region between the element isolation oxide films 506, inside the epitaxial area 504 by ion implantation of, for example, phosphorus. Furthermore, boron is ion-implanted into the epitaxial area 504 at an energy of 7 keV to form the intrinsic base region 509 in the epitaxial area 504.
Next, as shown in FIG. 7, a widow for forming an emitter region is made in the first oxide film 505. Phosphorus is then implanted into the epitaxial area 504 at an energy of 550 keV to form the pedestal collector 512 therein. Thereafter, the second conductive layer comprising polysilicon containing arsenic is grown on the whole surface to have a thickness of 250 nm. This is then patterned to form the emitter leading-out electrode 513 comprising the second conductive film on the opened window in the first oxide film 505.
Next, as shown in FIG. 8, a side wall 517 comprising an oxide film and having a thickness of 150 nm is formed on the side wall of the emitter leading-out electrode 513. Boron is ion-implanted therein at an energy of 10 keV to form the high-concentration P type diffusion layer 518, with self alignment, in the surface of the epitaxial area 504, using the emitter leading-out electrode 513 and the side wall 517 as masks. Subsequently, the resultant is subjected to RTA (Rapid Thermal Annealing) treatment, for example, at 1025xc2x0 C. for 20 seconds to diffuse arsenic from the emitter leading-out electrode 513, which is the second conductive film containing arsenic, into the intrinsic base region 509. The high-concentration N type diffusion layer 520 is formed in the intrinsic base region 509.
Next, as shown in FIG. 9, a known silicide technique is used to form the titanium silicide film 521, with self alignment, on the surface of the emitter leading-out electrode 513, the high-concentration P type diffusion layer 518 and the high-concentration N type diffusion layer 519.
Next, as shown in FIG. 10, the interlayer dielectric 522 is formed on the whole surface. The contact holes 526, 524 and 525 are made, at the positions corresponding to the emitter leading-out electrode 513, the high-concentration P type diffusion layer 518 and the high-concentration N type diffusion layer 519, in the interlayer dielectric 522. Thereafter, a contact plug 527 comprising a barrier metal composed of W and, for example, Ti/TiN is buried in the contact holes to form a pattern of a metal wiring 528 on the interlayer dielectric 522.
However, in the above-mentioned conventional bipolar transistor, the extrinsic base region composed of the high-concentration P type diffusion layer 518 and the titanium silicide film 521 is formed at both sides of the emitter electrode 513, and the base contact hole 524 for leading out base electrical potential is made in each of the extrinsic base regions. Therefore, the extrinsic base region, and the metal wirings 528 for leading out base electrical potential are present at both sides of the emitter electrode 513 so that the collector-base capacity Ccb cannot be made small. On the other hand, if the extrinsic base region (high-concentration P type diffusion layer 518) and the base contact hole 524 are disposed at only one side of the emitter electrode 513 to make the collector-base capacity Ccb small, the base resistance Rb increases. It is evident from the formula (1) that when the capacity Ccb or Rb increases in this way, the maximum oscillation frequency fmax drops to deteriorate the characteristics as a bipolar transistor. Accordingly, the conventional bipolar transistors have a problem that a sufficiently large maximum oscillation frequency cannot be obtained.
Thus, an object of the present invention is to provide a semiconductor device making it possible to reduce the base resistance Rb and the collector-base capacity Ccb to make the maximum oscillation frequency fmax sufficiently large and improve transistor characteristics, and a process for fabricating the same.
A first semiconductor device of the present invention comprises a first conduction type semiconductor substrate, a second conduction type area formed on a surface of the semiconductor substrate, a first conduction type intrinsic base region formed on a surface of the second conduction type area, an extrinsic base region surrounding the intrinsic base region, a second conduction type emitter region formed in the intrinsic base region, an emitter electrode contacting the emitter region, a second conduction type collector plug region formed in the second conduction type area, an element isolation area for isolating the first conduction type intrinsic base region and the extrinsic base region electrically from the second conduction type collector plug region, and a cobalt silicide film formed to surround the emitter electrode, as viewed from above, on the extrinsic base region.
A second semiconductor device of the present invention comprises a first conduction type semiconductor substrate, a second conduction type buried layer formed in the semiconductor substrate, a second conduction type epitaxial layer formed on the buried layer, a first conduction intrinsic base region formed on a surface of the epitaxial layer, an extrinsic base region surrounding the intrinsic base region, a second conduction type emitter region formed in the intrinsic base region, an emitter electrode contacting the emitter region, a second conduction type collector plug region formed on the buried layer, an element isolation area for isolating the intrinsic base region and the extrinsic base region electrically from the collector plug region, and a cobalt silicide formed to surround the emitter electrode, as viewed from above, on the extrinsic base region.
A third semiconductor device of the present invention comprises a first conduction type semiconductor substrate, second conduction type first and second well areas formed on a surface of the semiconductor substrate, a first conduction type third well area formed on the surface of the semiconductor substrate between the first and second well areas, a second conduction type MOS transistor formed in the first well area, a first conduction type MOS transistor formed on the third well area and a bipolar transistor formed in the second well area. Said bipolar transistor comprises a first conduction type intrinsic base region formed on the surface of the second well area, an extrinsic base region surrounding the intrinsic base region, a second conduction type emitter region formed in the intrinsic base region, an emitter electrode contacting the emitter region, a second conduction type collector plug region formed in the second conduction type area, an element isolation area for isolating the first conduction type intrinsic base region and the extrinsic base region electrically from the second conduction type collector plug region, and a cobalt silicide film formed to surround the emitter electrode, as viewed from above, on the extrinsic base region.
In these semiconductor devices, one base contact connected with the extrinsic base region is preferably arranged for the single emitter electrode.
A fourth semiconductor device of the present invention comprises a first conduction type semiconductor substrate, a second conduction type area formed on a surface of the semiconductor substrate, a pair of first conduction type intrinsic base regions formed on a surface of the second conduction type area, a first conduction type extrinsic base region formed to surround the intrinsic base regions as viewed from above, a second conduction type emitter region formed in the respective intrinsic base regions, a pair of emitter electrodes contacting the emitter region, a collector plug region formed in the second conduction type area, an element isolation area for isolating the extrinsic base region electrically from the collector plug region, and a cobalt silicide film formed to surround the respective emitter electrodes, as viewed from above, on the extrinsic base region.
This semiconductor device may comprise a pair of base contacts arranged in the extrinsic base region at both outsides of the emitter electrode and connected with the extrinsic base region, or a base contact area arranged in the extrinsic base region between the pair of the emitter electrodes and connected with the extrinsic base region.
A process for fabricating a semiconductor device of the present invention comprises the steps of forming an element isolation area for dividing a base formation planning area from a collector formation planning area, and a second conduction type area including these planning areas on a first conduction type silicon substrate; forming a first conduction type intrinsic base region on a surface of the second conduction type area of the base formation planning area; forming an insulating film on the whole surface thereof and making an opening in the emitter formation planning area of the insulating film; forming an emitter electrode comprising polysilicon film containing a second conduction type impurity on the insulating film to fill up in the opening of the insulating film; forming an emitter region contacting said emitter electrode in the intrinsic base region, forming an extrinsic base region surrounding the intrinsic base region in the intrinsic base region not converted with the emitter electrode, and forming a collector plug region in the collector formation planning area; forming a cobalt film on the whole surface and then reacting the cobalt film with the silicon of the substrate to form a cobalt silicide film; removing any unreacted cobalt film; forming an interlayer dielectric on the whole surface and then making contact holes at positions aligning with the cobalt silicide film in the emitter electrode and the extrinsic base region, and the cobalt silicide film in the collector leading-put area; and burying a conductive material in the contact holes to form contacts.
In the present invention, the cobalt silicide film is formed on the extrinsic base region to surround the periphery of the emitter electrode, and the contact contacting this cobalt silicide film is arranged at only one side of the emitter electrode. Any conventional titanium silicide film has a narrow line effect. Thus, if its width is made small, its layer resistance increase. Conventionally, wirings for leading out base voltage are arranged at both sides of the emitter electrode to lower the base resistance as much as possible. Therefore, in conventional bipolar transistors, the width of the titanium silicide film 521 on the high-concentration P type diffusion layer 518 cannot be made narrow. This is a reason why the distance between the emitter electrode 513 and the field insulating film 506 cannot be made small and the collector-base capacity Ccb cannot be reduced.
On the other hand, in the present invention, the cobalt silicide film is used instead of the titanium silicide and further the cobalt silicide film is formed in a ring form so as to surround the emitter electrode. The resistance when an electric current is passed from the intrinsic base region to the cobalt silicide film through the extrinsic base region, that is, the resistance when an electric current is passed in a vertical direction, is larger than the corresponding resistance in the case of using the titanium silicide. Therefore, even if the contact is disposed at only one side of the emitter electrode as in the present embodiment, the base resistance Rb can be made sufficiently small. Since the contact and the wiring connecting with it are formed at only one side of the emitter electrode, the distance between the emitter electrode and the filed insulating film, that is, the width of the base region, can be made small so that the collector-base capacity Ccb can be made small. According to the present invention, therefore, the maximum oscillation frequency fmax can be improved to improve transistor characteristics.